Administrivia

• First off, be safe/healthy!
• Last miles:
  1. Virtual final project demo/presentation: 7 to 10-min video (DUE: Apr 13)
  2. Final project peer-evaluation (DUE: Apr 14/Apr 15)
  3. Final write-up/code (DUE: May 1)
  4. Quiz #2 will be distributed at 9am on Apr 21 (take-home/open-ended, 24h)
  5. Lab4 (DUE: Apr 20 w/ 2-week late days)

About Quiz 2

• I will prepare “review materials” for Quiz #2 (on Apr 9)
• Topics include Lab 1-4 and Lec 1-17 (not Lab5 and Lec 18/19)
• 24h, so no rustling-type questions but open-ended/book questions

Q&A

What happens when the processor doesn’t know how to handle the exception?

Are Synchronous Interrupts possible, or are they all asynchronous?

Agenda

• LEC 15: Interrupt and Exception (Lab4, Phase 1)
• LEC 16: Process and Scheduling (Lab4, Phase 2)
• LEC 17: Virtual Memory (Lab4, Phase 3/4)
• LEC 19/20: Synchronization (Lab5, Phase 1)

Summary: Exception level / Execution states

• A logical separation of software execution privilege
  • Similar to hierarchical protection domains (e.g., ring in x86)

Execution states of AArch32/64

Changing execution levels (target mode)

• When a processor takes an exception (e.g., interrupt or system call):
  1. Save the current processor state in SPSR
  2. Save the return address to ELR

Example: invoking a system call

Today topic: exception handling (in Arm)

• Exception: system events requiring an action/service by the kernel (link)
  • Asynchronous: e.g., external events/signal (aka, interrupt)
  • Synchronous: e.g., svc (system call), data abort (access violation), etc.

Example: actions/events causing an exception

• Abort: instruction or data aborts (access violation)
• Exception generating instructions: supervisor call (svc), hypervisor call (hvc)
• Interrupt: IRQ, FIQ (e.g., timer/usb interrupt in lab4/5)

Note on definition (x86)

• Interrupt: asynchronous events (i.e., any moment)
• Exception: synchronous events (i.e., instruction boundary)
  • fault: faulting instruction not executed (e.g., page fault)
  • trap: trapping instruction executed (e.g., break point)
  • abort: no way to recover (e.g., machine check, double fault)

-> Interrupt in x86: a control transfer mechanism

Interrupt routing (RPi3)

Handling synchronous exceptions

• Two information provided for a synchronous exception:
  • ESR_ELn: Exception Syndrome Register
  • FAR_ELn: Fault Address Register

Handling synchronous exceptions

• ESR_ELn.EC: Exception class (e.g., alignment, data abort)
• ESR_ELn.IL: Instruction length (e.g., 1 for 32-bit)
• ESR_ELn.ISS: Instruction Specific Syndrome (e.g., translation level)

Example: invoking a system call (workflow)

Example: invoking a system call (in kernel)

#[no_mangle]
pub extern "C" fn handle_exception(info: Info, esr: u32, 
                                   tf: &mut TrapFrame) {
    match info.kind {
        Kind::Synchronous => {
            let syndrome = Syndrome::from(esr);
            match syndrome {
                Syndrome::Brk(_) => { ... }
                Syndrome::Svc(n) => {
                    handle_syscall(n, tf);
                    return;
                }
                ...
        },
        ...
    }
}

Example: invoking a system call (in kernel)

// (ref: D1.10.4)
pub enum Syndrome {
    Unknown,
    SimdFp,
    IllegalExecutionState,
    Svc(u16),
    Hvc(u16),
    Smc(u16),
    InstructionAbort { kind: Fault, level: u8 },
    PCAlignmentFault,
    DataAbort { kind: Fault, level: u8 },
    SpAlignmentFault,
    Breakpoint,
    Step,
    Watchpoint,
    Brk(u16),
    Other(u32),
    ...
}

Synchronous exception in other exception levels

Exception handling steps

1. PSTATE → SPSR_ELn (where n is the exception level where the exception is taken)
2. PC → ELR_ELn
3. PSTATE is updated for an exception handler (i.e., PC and SP)

Nested exception handling steps

Exception vector table

• Vector means to direct an interrupt to a certain entry in the table
• 4 (exception types) x 4 (execution modes) = 16 entries
  • Each entry contains 0x80 bytes of the actual code (unlike a pointer)
  • PC will be updated based on a combinations of two conditions
• VBAR_EL1: points to the vector table

Exception vector table

• Exception types
  1. Synchronous: e.g., used for handling system calls
  2. IRQ: used for handling timer interrupt (in Lab3)
  3. FIQ: used for handling USB interrupt (in Lab5)
  4. SError: not supported

pub enum Kind {
    Synchronous = 0,
    Irq = 1,
    Fiq = 2,
    SError = 3,
}

Exception vector table

• Execution modes
  1. Current EL with SP0 (not supported)
  2. Current EL with SPx: e.g., when data abort in your kernel
  3. Lower EL using AArch64: e.g., a syscall from userspace
  4. Lower EL using AArch32 (not supported)

pub enum Source {
    CurrentSpEl0 = 0,
    CurrentSpElx = 1,
    LowerAArch64 = 2,
    LowerAArch32 = 3,
}

Exception vector table

.align 11
.global vectors
vectors:
    HANDLER 0, 0
    HANDLER 0, 1
    HANDLER 0, 2
    HANDLER 0, 3
    ...
    HANDLER 3, 3

Exception vector table (vector.s)

.macro HANDLER source, kind
    .align 7
    stp     lr, xzr, [SP, #-16]!
    stp     x28, x29, [SP, #-16]!
    
    mov     x29, \source
    movk    x29, \kind, LSL #16
    bl      context_save
    
    ldp     x28, x29, [SP], #16
    ldp     lr, xzr, [SP], #16
    eret
.endm

Returning from an exception (reverse)

• Upon eret (lowering the exception level):
  1. SPSR_ELn → PSTATE (where n is the exception level where the exception is taken)
  2. ELR_ELn → PC

Processor state (PSTATE)

• Conditional flags: N, Z, C, V
• Interrupt masks: D (Debug), A (SError), I (IRQ), F (FIQ)
• Execution state: nRW (32/64-bit)
• Stack selection: SP (SP_EL0/SP_ELn)
• Misc: SS (single step), IL (illegal execution)

Controlling interrupts

MSR DAIFSet, #Imm4  // Used to set any or all of DAIF to 1
MSR DAIFClr, #Imm4  // Used to clear any or all of DAIF to 0

/// Enable (unmask) IRQ interrupts
pub fn enable_irq_interrupt() {
    unsafe {
        asm!("msr DAIFClr, 0b0010" :::: "volatile");
    }
}
/// Disable (mask) FIQ interrupt
pub fn disable_fiq_interrupt() {
    unsafe { 
        asm!("msr DAIFSet, 0b0001" :::: "volatile");
    }
}

Interrupt handling

Nested interrupt handling (same EL)

Interrupt handling routines

#[no_mangle]
pub extern "C" fn handle_exception( ... ) {
    match info.kind {
        Kind::Synchronous => {
            let syndrome = Syndrome::from(esr);
            match syndrome {
                Syndrome::Brk(_) => { ... }
                Syndrome::Svc(n) => { ... }
        }
        Kind::Irq => {
            let ic = Controller::new();
            for v in Interrupt::iter() {
                if ic.is_pending(v) {
                    crate::IRQ.invoke(v, tf);
                }
            }
        }
        ...
}

Summary: Exception/interrupt

• Exception is a way to transfer a control to higher-privileged component
  • e.g., requesting a service for an interrupt
  • e.q., requesting a software service like file system accesses via system calls
• Two types: synchronous and asynchronous
• Carefully enabling/disabling based on execution conditions

References

• Fundamentals of ARMv8-A
• AArch64 Exception and Interrupt Handling
• Linux on AArch64 ARM 64-bit Architecture